AMD today announced further plans to innovate the x86 architecture byintroducing SSE5, a new extension of the x86 instruction set that is designed toallow software developers to simplify code and achieve greater efficiency forthe most performance-hungry applications. SSE5 will give developers additionalcapabilities to help maximize the performance of applications that have dailyimpact on consumers and enterprises, including high performance computing,multimedia and security applications. By making the SSE5 specification availableto developers today, AMD expects to ease the adoption of the new instructionsfor tool providers and software vendors who develop these performance-intenseapplications.
Chip advancements and software improvements go hand-in-hand, to the benefit ofconsumers and enterprises alike," said Phil Hester, senior vice president andchief technology officer, AMD. "The impact of our designs are best realized whenAMD-based servers, PCs and devices enable software to more effectively solveevery-day problems and enhance every-day experiences. By announcing our plans toadd SSE5 instructions to the x86 instruction set -- and by making thespecification available today -- we are enabling open and collaborative softwareinnovation that will bring AMD's advancements to life for our customers andend-users."
As the industry's focus is shifting from processor speeds to increasing powerefficiency, the number of instructions executed per second on one processor coreremains relatively constant. As a result, both software and hardware vendorsmust pursue new approaches to improving computing performance.
AMD is once again helping advance this process by making technical detailsavailable to the software developer community early, to foster an industrydialogue and solicit feedback. For example, AMD released an early version of theAMD Virtualization(TM) specification in 2005, at the time codenamed "Pacifica,"to the benefit of that technology's further development. Additionally, AMDrecently released the Light-Weight Profiling proposal, which is designed toenable software developers to fully leverage the benefits of multi-corecomputing. The early release of the SSE5 specification to the software developercommunity follows AMD's philosophy of open collaboration, a model thateffectively drove x86, 64-bit computing to the masses.
"PGI's goal is to provide high-performance, cross-platform, production-qualityparallel compilers and software development tools to the developer community,"said Douglas Miles, director, The Portland Group. "We are working closely withAMD to enable developers to quickly and easily leverage the SSE5 instruction setto enhance high performance computing, and the multi-core and multi-mediacapability of their software applications."
Multi-core processor technology and the integration of specialized co-processorsare effective methods for extending performance limits. Equally important isenabling the ability to maximize the efficiency of each core by reducing thetotal number of instructions needed to achieve the same result. SSE5 helpsmaximize the output of each instruction and consolidates code base byintroducing functionality previously only found in specialized, high-performancearchitectures, to the x86 platform:
3-Operand Instructions
A computing instruction is executed by applying a mathematical or logicalfunction to operands, or inputs. By increasing the number of operands an x86instruction can handle from 2 to 3, SSE5 enables the consolidation of multiple,simple instructions into a single, more effective instruction. The ability toexecute 3-Operand Instructions is currently only possible on certain RISCarchitectures.
Fused Multiply Accumulate
The 3-Operand Instruction capability enables the creation of new instructionswhich efficiently execute complex calculations. The Fused Multiply Accumulateinstruction combines multiplication and addition to enable iterativecalculations with one instruction. The simplification of the code enables rapidexecution for more realistic graphics shading, rapid photographic rendering,spatialized audio, complex vector mathematics and other performance-intenseapplications.
The SSE5 specification, which is being made available to the developer communitytoday at http://developer.amd.com/SSE5,will be implemented in products based on AMD's next-generation "Bulldozer" core,available in 2009.
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